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           科技部博士後研究人員學術著作獎作品

    • [1]　First demonstration of flash RRAM on pure CMOS logic 14nm FinFET platform featuring excellent immunity to sneak-path and MLC capability

      •      IEEE EDS舉辦國際會議- IRPS, IPFA, EDTM, VLSI-TSA, SSDM, & SNW

    • [1]　A Novel Physical Unclonable Function: NBTI-PUF Realized by Random Trap Fluctuation (RTF) Enhanced True Randomness in 14 nm FinFET Platform
    • [2]　A Built-in Spice Time-domain Variation Model of the BTI-induced Random Trap Fluctuation (RTF) in 14 nm FinFETs
    • [3]　FinFET Plus: A Scalable FinFET Architecture with 3D Air-Gap and Air-Spacer Toward the 3nm Generation and Beyond
    • [4]　Fin-TFET: Design of FinFET-based Tunneling FET with Face-tunneling Mechanism
    • [5]　A Reliable Triple-Level Operation of Resistive-Gate Flash Featuring Forming-Free and High Immunity to Sneak Path
    • [6]　A Pulsed RTN Transient Measurement Technique: Demonstration on the Understanding of the Switching in Resistance Memory
    • [7]　Design of Low Voltage Vertical Channel Face-tunneling TFET Using Ge/SiGe Materials and Its SRAM Circuit Performance
    • [8]　A Self-align Gate-last Resistive Gate Switching FinFET Nonvolatile Memory Feasible for Embedded Applications
    • [9]　The Guideline on Designing a High Performance NC MOSFET by Matching the Gate Capacitance and Mobility Enhancement
    • [10]　A Novel Experimental Approach to Extracting Negative Capacitances: Newly found Negative DIBL Effect in 14nm NC-FinFET and the Way to Achieve Hysteresis-free
    • [11]　A novel rewritable one-time-programming OTP (RW-OTP) realized by dielectric-fuse RRAM devices featuring ultra-high reliable retention and good endurance for embedded applications
    • [12]　A Novel Approach to Localize the Channel Temperature Induced by the Self-heating Effect in 14nm High-k Metal-gate FinFET
    • [13]　The Experimental Observations of a New Dielectric-fuse Breakdown in a Bilayer-RRAM to Realize the OTP Functionality
    • [14]　The impact of TiN barrier on the NBTI in an advanced high-k metal-gate p-channel MOSFET
    • [15]　The issues on the power consumption of trigate FinFET: The design and manufacturing guidelines
    • [16]　The guideline on designing face-tunneling FET for large-scale-device applications in IoT
    • [17]　A novel design of P-N staggered face-tunneling TFET targeting for low power and appropriate performance applications
    • [18]　Geometric variation: A novel approach to examine the surface roughness and the line roughness effects in trigate FinFETs

      •      固態組國際頂級旗艦會議- IEDM & Symposia on VLSI 計十篇

    • [1]　NVDimm-FE: A High-density 3D Architecture of 3-bit/c 2TnCFE to Break Great Memory Wall with 10 ns of PGM-pulse, 1010 Cycles of Endurance, and Decade Lifetime at 103 °C
    • [2]　The First Embedded 14nm FeFinFET NVM: 2T1CFE Array as Electrical Synapses and Activations for High-performance and Low-power Inference Accelerators
    • [3]　A Novel Complementary Architecture of One-time-programmable Memory and Its Applications as Physical Unclonable Function (PUF) and One-time Password
    • [4]　Novel Concept of Hardware Security in Using Gate-switching FinFET Nonvolatile Memory to Implement True-Random-Number Generator
    • [5]　High-Density Multiple Bits-per-Cell 1T4R RRAM Array with Gradual SET/RESET and its Effectiveness for Deep Learning
    • [6]　Novel Concept of the Transistor Variation Directed Toward the Circuit Implementation of Physical Unclonable Function (PUF) and True-random-number Generator (TRNG)
    • [7]　A Novel Architecture to Build Ideal-linearity Neuromorphic Synapses on a Pure Logic FinFET Platform Featuring 2.5ns PGM-time and 1012 Endurance
    • [8]　The Demonstration of Gate Dielectric-fuse 4kb OTP Memory Feasible for Embedded Applications in High-k Metal-gate CMOS Generations and Beyond
    • [9]　Embedded PUF on 14nm HKMG FinFET Platform: A Novel 2-bit-per-cell OTP-based Memory Feasible for IoT Secuirty Solution in 5G Era
    • [10]　An Energy Efficient FinFET-based Field Programmable Synapse Array (FPSA) Feasible for One-shot Learning on EDGE AI

      •      DSML      發表論文一覽

    • [1]　Positive-bias-temperature-instability Induced Random-trap-fluctuation Enhanced Physical Unclonable Functions on 14-nm nFinFETs
    • [2]　Cryogenic Quasi-Ballistic Transport Enhanced by Strained Silicon Technologies in 14-nm Complementary Fin Field Effect Transistors Through Virtual Source Model
    • [3]　A three-bit-per-cell via-type resistive random access memory gated metal-oxide semiconductor field-effect transistor non-volatile memory with the FORMing-free characteristic
    • [4]　An Embedded Three-Bit-Per-Cell Two-Transistors and One-Ferroelectric-Capacitance Nonvolatile Memory
    • [5]　RADAR: A Fast and Energy-Efficient Programming Technique for Multiple Bits-Per-Cell RRAM Arrays
    • [6]　A FORMing-Free HfO2-/HfON-Based Resistive-Gate Metal–Oxide–Semiconductor Field-Effect-Transistor (RG-MOSFET) Nonvolatile Memory With 3-Bit-Per-Cell Storage Capability
    • [7]　Four-Bits-Per-Memory One-Transistor-and-Eight-Resistive-Random-Access-Memory (1T8R) Array
    • [8]　An Experimental Approach to Characterizing the Channel Local Temperature Induced by Self-Heating Effect in FinFET
    • [9]　A 14-nm FinFET Logic CMOS Process Compatible RRAM Flash With Excellent Immunity to Sneak Path
    • [10]　Principles and Applications of Ig-RTN in Nano-scaled MOSFET
    • [11]　A FORMing-Free HfO2-/HfON-Based Resistive-Gate Metal–Oxide–Semiconductor Field-Effect-Transistor (RG-MOSFET) Nonvolatile Memory With 3-Bit-Per-Cell Storage Capability
    • [12]　Four-Bits-Per-Memory One-Transistor-and-Eight-Resistive-Random-Access-Memory (1T8R) Array
    • [13]　An Experimental Approach to Characterizing the Channel Local Temperature Induced by Self-Heating Effect in FinFET
    • [14]　A 14-nm FinFET Logic CMOS Process Compatible RRAM Flash With Excellent Immunity to Sneak Path
    • [15]　A theoretical and experimental evaluation of surface roughness variation in trigate metal oxide semiconductor field effect transistors
    • [16]　The understanding on the evolution of stress-induced gate leakage in high-k dielectric metal-oxide-field-effect transistor by random-telegraph-noise measurement
    • [17]　The understanding of the drain-current fluctuation in a silicon-carbon source-drain strained n-channel metal-oxide-semiconductor field-effect transistors
    • [18]　The mechanisms of random trap fluctuation in metal oxide semiconductor field effect transistors
    • [19]　Suppressing Device Variability by Cryogenic Implant for 28-nm Low-Power SoC Applications
    • [20]　The proximity of the strain induced effect to improve the electron mobility in a silicon-carbon source-drain structure of n-channel metal-oxide-semiconductor field-effect transistors
    • [1]　A Novel Complementary Architecture of One-time- programmable Memory and Its Applications as Physical Unclonable Function (PUF) and One-time Password
    • [22]　Novel Concept of Hardware Security in Using Gate- switching FinFET Nonvolatile Memory to Implement True-Random-Number Generator
    • [23]　High-Density Multiple Bits-per-Cell 1T4R RRAM Array with Gradual SET/RESET and its Effectiveness for Deep Learning
    • [24]　Novel Concept of the Transistor Variation Directed Toward the Circuit Implementation of Physical Unclonable Function (PUF) and True-random-number Generator (TRNG)
    • [25]　A Novel Architecture to Build Ideal-linearity Neuromorphic Synapses on a Pure Logic FinFET Platform Featuring 2.5ns PGM-time and 1012 Endurance
    • [26]　The Demonstration of Gate Dielectric-fuse 4kb OTP Memory Feasible for Embedded Applications in High-k Metal-gate CMOS Generations and Beyond
    • [27]　Embedded PUF on 14nm HKMG FinFET Platform: A Novel 2-bit-per-cell OTP-based Memory Feasible for IoT Security Solution in 5G Era
    • [28]　An Energy Efficient FinFET-based Field Programmable Synapse Array (FPSA) Feasible for One-shot Learning on EDGE AI
    • [29]　First demonstration of flash RRAM on pure CMOS logic 14nm FinFET platform featuring excellent immunity to sneak-path and MLC capability
    • [30]　A new variation plot to examine the interfacial-dipole induced work-function variation in advanced high-k metal-gate CMOS devices
    • [31]　The demonstration of low-cost and logic process fully-compatible OTP memory on advanced HKMG CMOS with a newly found dielectric fuse breakdown
    • [32]　A circuit level variability prediction of basic logic gates in advanced trigate CMOS technology
    • [33]　The experimental demonstration of the BTI-induced breakdown path in 28nm high-k metal gate technology CMOS devices
    • [34]　Gate current variation: A new theory and practice on investigating the off-state leakage of trigate MOSFETs and the power dissipation of SRAM
    • [35]　The understanding of multi-level RTN in trigate MOSFETs through the 2D profiling of traps and its impact on SRAM performance: A new failure mechanism found
    • [36]　The understanding of the trap induced variation in bulk tri-gate devices by a novel random trap profiling (RTP) technique
    • [37]　A novel and direct experimental observation of the discrete dopant effect in ultra-scaled CMOS devices
    • [38]　A new and simple experimental approach to characterizing the carrier transport and reliability of strained CMOS devices in the quasi-ballistic regime
    • [39]　Design of high-performance and highly reliable nMOSFETs with embedded Si:C S/D extension stressor(Si:C S/D-E)
    • [40]　A new observation of strain-induced slow traps in advanced CMOS technology with process-induced strain using random telegraph noise measurement
    • [41]　FinFET Plus: A Scalable FinFET Architecture with 3D Air-Gap and Air-Spacer Toward the 3nm Generation and Beyond
    • [42]　A Reliable Triple-Level Operation of Resistive-Gate Flash Featuring Forming-Free and High Immunity to Sneak Path
    • [3]　Design of Low Voltage Vertical Channel Face-tunneling TFET Using Ge/SiGe Materials and Its SRAM Circuit Performance
    • [44]　A Self-align Gate-last Resistive Gate Switching FinFET Nonvolatile Memory Feasible for Embedded Applications
    • [45]　A Pulsed RTN Transient Measurement Technique: Demonstration on the Understanding of the Switching in Resistance Memory
    • [46]　The understanding of gate capacitance matching on achieving a high performance NC MOSFET with sufficient mobility
    • [47]　The Guideline on Designing a High Performance NC MOSFET by Matching the Gate Capacitance and Mobility Enhancement
    • [48]　The Design of High Performance Si/SiGe-Based Tunneling FET: Strategies and Solutions
    • [49]　A novel rewritable one-time-programming OTP (RW-OTP) realized by dielectric-fuse RRAM devices featuring ultra-high reliable retention and good endurance for embedded applications
    • [50]　A novel approach to localize the channel temperature induced by the self-heating effect in 14nm high-k metal-gate FinFET
    • [51]　The impact of TiN barrier on the NBTI in an advanced high-k metal-gate p-channel MOSFET
    • [52]　The issues on the power consumption of trigate FinFET: The design and manufacturing guidelines
    • [53]　The guideline on designing face-tunneling FET for large-scale-device applications in IoT
    • [54]　A novel design of P-N staggered face-tunneling TFET targeting for low power and appropriate performance applications
    • [55]　Geometric variation: A novel approach to examine the surface roughness and the line roughness effects in trigate FinFETs
    • [56]　Experimental techniques on the understanding of the charge loss in a SONOS nitride-storage nonvolatile memory
    • [57]　A novel one transistor resistance-gate nonvolatile memory
    • [58]　A novel one transistor non-volatile memory feasible for NOR and NAND applications in IoT era
    • [59]　An Innovative 1T1R Dipole Dynamic Random Access Memory (DiRAM) featuring high speed, ultra-low power, and low voltage operation
    • [60]　The RTN measurement technique on leakage path finding in advanced high-k metal gate CMOS devices
    • [61]　Design of complementary tilt-gate TFETs with SiGe/Si and III-V integrations feasible for ultra-low-power applications
    • [62]　A comprehensive transport model for high performance HEMTs considering the parasitic resistance and capacitance effects
    • [63]　The observation of BTI-induced RTN traps in inversion and accumulation modes on HfO2 high-k metal gate 28nm CMOS devices
    • [64]　The understanding of the bulk trigate MOSFET's reliability through the manipulation of RTN traps
    • [65]　The impact of the carrier transport on the random dopant induced drain current variation in the saturation regime of advanced strained-silicon CMOS devices
    • [66]　New criteria for the RDF induced drain current variation considering strain and transport effects in strain-silicon CMOS devices
    • [67]　Experimental determination of the transport parameters in high performance Dopant-Segregated Schottky-barrier MOSFETs
    • [68]　New observations on the physical mechanism of Vth-variation in nanoscale CMOS devices after long term stress
    • [69]　The understanding of strain-induced device degradation in advanced MOSFETs with process-induced strain technology of 65nm node and beyond
    • [70]　The investigation of the stress-induced traps and its correlation to PBTI in high-kdielectrics nMOSFETs by the RTN measurement technique
    • [71]　New observation of an abnormal leakage current in advanced CMOS devices with short channel lengths down to 50nm and beyond
    • [72]　The ballistic transport and reliability of the SOI and strained-SOI nMOSFETs with 65nm node and beyond technology
    • [73]　Nonvolatile resistance memory and its operation thereof
    • [74]　記憶體陣列電路
    • [75]　非揮發性電阻式記憶體及其操作
    • [76]　Staggered-type Tunneling Field Effect Transistor
    • [77]　交錯行穿隧場效晶體管
    • [78]　Nand Type Variable Resistance Random Access Memory and Methods
    • [79]　一種非揮發性阻變式儲存電路及其控制方法
    • [80]　一種反及型態阻變式快閃記憶體電路及操作
    • [81]　Structure and Formation Method of Semiconductor Device Structure
    • [82]　半導體裝置結構
    • [83]　半導體元件裝置
    • [84]　Structure and Formation Method of Semiconductor Device Structure
    • [85]　半導體裝置結構
    • [86]　半導體裝置結構
    • [87]　Dielectric Fuse Memory Circuit and Operation Method Thereof
    • [88]　介電質熔絲記憶電路及其操作方法
    • [89]　Nonvolatile Memory and Its Operation Method Thereof
    • [90]　非揮發性記憶體與其操作方法
    • [91]　非揮發性記憶體與其操作方法
    • [92]　Nonvolatile Memory Comprising Variable Resistance Transistors and Method for Operating the Same
    • [93]　三閘極場效電晶體

    • 技術報告暨其他

           技術報告

    • [1]　謝易叡 著，《國防科技前瞻_未來國防科技發展建議-技術報告: 應對5G-AIOT應用廣泛興起所導致資安議題的量子硬體防護解決方案》， 工研院，已被接受尚未出刊，一零九年。